PXS20RM Datasheet, PDF (554/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flash Memory
23.1.5.1 C90FL Read and Write
The default state of the C90FL module is read. The main and shadow address space can be read only in
the read state. The Module Configuration Register (MCR) is always available for read. The C90FL module
enters the read state on reset. The C90FL module is in the read state under four sets of conditions:
• The read state is active when PGM=1 or ERS=1 in the MCR (Read While Write)
NOTE
Reads done to the partition(s) being operated on (either erased or
programmed) will result in an error and the RWE bit in the MCR will be set.
• The read state is active when PGM=1 and PSUS=1 in the MCR. (Program suspend)
• The read state is active when ERS=1 and ESUS=1 and PGM=0 in the MCR. (Erase suspend)
NOTE
FC reads are done through the BIU. In many cases the BIU will do “page
buffering” to allow sequential reads to be done with higher performance.
This can create a Data Coherency issue that must be handled with software.
Data Coherency can be an issue after a program or erase operation, as well
as shadow row operations.
In C90FL user mode, registers can be written. Array can be written to do interlock writes.
Reads attempted to invalid locations will result in indeterminate data. Invalid locations occur when
addressing is done to blocks that do not exist in non 2ⁿ array sizes.
Interlock writes attempted to invalid locations (due to blocks that do not exist in non 2ⁿ array sizes), will
result in an interlock occurring, but attempts to program or erase these blocks will not occur since they are
forced to be locked.
23.1.5.2 Read While Write (RWW)
The Flash Core is divided into partitions. Partitions always comprise two or more blocks. Partitions are
used to determine Read While Write (RWW) groupings. While a write (program or erase) is being done
within a given partition, a read can be simultaneously executed to any other partition. Partitions are listed
in Table 23-1. Note that the shadow block has unique Read While Write restrictions described in
Section 23.1.5.8, C90FL Shadow Block.
The FC is also divided into blocks to implement independent erase or program protection. The shadow
block exists outside the normal address space and is programmed, erased and read independently of the
other blocks. The shadow block is included to support systems that require NVM for security or system
initialization information.
A software mechanism is provided to independently lock or unlock each block in high, mid, and low
address space against program and erase. In addition, two hardware locks are provided to enable/disable
the FC for program/erase. See Section 23.1.5.4, Software Locking, for more information.
23-4
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor