PXS20RM Datasheet, PDF (1151/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Periodic Interrupt Timer (PIT)
36.3.2 Register descriptions
This section describes in address order all the PIT registers and their individual bits.
36.3.2.1 PIT Module Control Register (PITMCR)
This register controls whether the timer clocks should be enabled and whether the timers should run in
debug mode.
Offset 0x000
Access: Read/Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
MDIS FRZ
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 36-2. PIT Module Control Registers (PITMCR)
Field
MDIS
FRZ
Table 36-3. PITMCR Field Descriptions
Description
Module Disable. This is used to disable the module clock. This bit should be enabled before any other
setup is done.
0 Clock for PIT Timers is enabled (default)
1 Clock for PIT Timers is disabled
Freeze. Allows the timers to be stopped when the device enters debug mode.
0 = Timers continue to run in debug mode.
1 = Timers are stopped in debug mode.
36.3.2.2 Timer Load Value Register (LDVAL)
These registers select the timeout period for the timer interrupts.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
36-3