PXS20RM Datasheet, PDF (756/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
26.5.2.30 Offset Correction Value Register (FR_OFCORVR)
Base + 0x003A
Additional Reset: RUN Command
0
R
W
Rese
t
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
OFFSETCORR
000000000000000
Figure 26-30. Offset Correction Value Register (FR_OFCORVR)
This register provides the sign extended offset correction value in microticks as it was calculated by the
clock synchronization algorithm. The CC updates this register during the NIT.
Table 26-35. FR_OFCORVR Field Descriptions
Field
OFFSET-
CORR
Description
Offset Correction Value — protocol related variable: vOffsetCorrection (before value limitation
and external offset correction)
This field provides the sign extended offset correction value in microticks as it was calculated by
the clock synchronization algorithm. The value is represented in 2’s complement format. This value
does not include the value limitation and the application of the external offset correction. If the
magnitude of the internally calculated rate correction value exceeds the limit given by
offset_correction_out field in the Protocol Configuration Register 29 (FR_PCR29), the clock
correction reached limit interrupt flag CCL_IF is set in the Protocol Interrupt Flag Register 0
(FR_PIFR0).
Note: If the CC was not able to calculate an new offset correction term due to a lack of
synchronization frames, the OFFSETCORR value is not updated.
26.5.2.31 Combined Interrupt Flag Register (FR_CIFR)
Base + 0x003C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
MIF
PRIF
CHIF
WUP
IF
FAFB
IF
FAFA
IF
RBIF
TBIF
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-31. Combined Interrupt Flag Register (FR_CIFR)
This register provides five combined interrupt flags and a copy of three individual interrupt flags. The
combined interrupt flags are the result of a binary OR of the values of other interrupt flags regardless of
the state of the interrupt enable bits. The generation scheme for the combined interrupt flags is depicted in
Figure 26-162. The individual interrupt flags WUPIF, FAFBIF, and FAFAIF are copies of corresponding
flags in the Global Interrupt Flag and Enable Register (FR_GIFER) and are provided here to simplify the
application interrupt flag check. To clear the individual interrupt flags, the application must use the Global
Interrupt Flag and Enable Register (FR_GIFER).
26-44
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor