PXS20RM Datasheet, PDF (1292/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Semaphore Unit (SEMA4)
Table 43-6. SEMA4_RSTNTF field descriptions
Field
Description
RSTNSM
RSTNMS
Reset Notification Finite State Machine. The reset state machine is maintained in a 2-bit, three-state
implementation, defined as:
00 Idle, waiting for the first data pattern write.
01 Waiting for the second data pattern write.
10 The two-write sequence has completed. Generate the specified notification reset(s). After the
reset is performed, this machine returns to the idle (waiting for first data pattern write) state.
11 This state encoding is never used and therefore reserved.
Reads of the SEMA4_RSTNTF register return the encoded state machine value. Note the RSTNSM
= 0b10 state is valid for a single machine cycle only, so it is impossible for a read to return this value.
Reset Notification Bus Master. This 3-bit read-only field records the logical number of the bus master
performing the notification reset function. The reset function requires that the two consecutive writes
to this register be initiated by the same bus master to succeed. This field is updated each time a write
to this register occurs.
Master
e200z4d_0
e200z4d_1
eDMA
FlexRay
—
—
—
—
Master ID
0
1
2
3
4
5
6
7
RSTNTN
RSTNDP
Reset Notification Number. This 8-bit field specifies the specific IRQ notification state machine to be
reset. This field is updated by the second write.
If RSTNTN < 64, then reset the single IRQ notification machine defined by RSTNTN, else reset all the
notifications.
Reset Notification Data Pattern. This write-only field is accessed with the specified data patterns on
the two consecutive writes to enable the notification reset mechanism. For the first write, RSTNDP =
0x47 while the second write requires RSTNDP = 0xb8.
43.4 Functional description
Multi-processor systems require a function that can be used to safely and easily provide a locking
mechanism that is then used by system software to control access to shared data structures, shared
hardware resources, and etc. These gating mechanisms are used by the software to serialize (and
synchronize) writes to shared data and/or resources to prevent race conditions and preserve memory
coherency between processes and processors.
For example, if processor X enters a section of code where shared data values are to be updated or read
coherently, it must first acquire a semaphore. This locks, or closes, a software gate. After the gate has been
locked, a properly architected software system does not allow other processes (or processors) to execute
the same code segment or modify the shared data structure protected by the gate, that is, other
43-10
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor