PXS20RM Datasheet, PDF (646/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexCAN Module
– Determine the bit rate by programming the PRESDIV field
– Determine the internal arbitration mode (LBUF bit)
• Initialize the Message Buffers
– The Control and Status word of all Message Buffers must be initialized
– If FIFO was enabled, the 8-entry ID table must be initialized
– Other entries in each Message Buffer should be initialized as required
• Initialize the Rx Individual Mask Registers
• Set required interrupt mask bits in the IMASK Registers (for all MB interrupts), in CTRL Register
(for Bus Off and Error interrupts) and in MCR Register for Wake-Up interrupt
• Negate the HALT bit in MCR
Starting with the last event, FlexCAN attempts to synchronize to the CAN bus.
24.5.2 FlexCAN addressing and RAM size configurations
The RAM configuration is as follows:
• 544 bytes for MB memory
• 128 bytes for Individual Mask Registers
In each configuration the user can program the maximum number of MBs that will take part in the
matching and arbitration processes using the MAXMB field in the MCR Register. MAXMB can be any
number between 0–31.
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PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor