PXS20RM Datasheet, PDF (1296/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Semaphore Unit (SEMA4)
cores. For PowerPC cores, there is a processor ID register (PIR) which is SPR 286 and contains this value.
A single instruction can be used to move the contents of the PIR into a general-purpose register: mfspr
rx,286 where rx is the destination GPRn. Other architectures may support a specific instruction to move
the contents of the logical processor number into a general-purpose register, e.g., rdcpn rx for a read
CPU number instruction.
If the optional failed lock IRQ notification mechanisms are used, then accesses to the related registers
(SEMA4_CPnINE, SEMA4_ CPnNTF) are required. There is no required negation of the failed lock write
notification interrupt as the request is automatically negated by the SEMA4 unit once the gate has been
successfully locked by the failing processor.
Finally, in the event a system state requires a software-controlled reset of a gate or IRQ notification
register(s), accesses to the secure reset control registers (SEMA4_RSTGT, SEMA4_RSTNTF) are
required. For these situations, it is recommended that the appropriate IRQ notification enable(s)
(SEMA4_CPnINE) bits be disabled before initiating the secure reset 2-write sequence to avoid any race
conditions involving spurious notification interrupt requests.
43.7 DMA requests
There are no DMA requests associated with the SEMA4 unit.
43-14
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor