PXS20RM Datasheet, PDF (1169/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Address
0xC3FE
_8080
…
0xC3FE
_80FC
0xC3FE
_8100
…
0xC3FE
_BFFC
Power Control Unit (MC_PCU)
Table 38-2. MC_PCU Memory Map (continued)
Name
0 1 2 3 27 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
PMU registers
reserved
38.3.2 Register Descriptions
All registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered
according to big endian. For example, the PD0 field of the PCU_PSTAT register may be accessed as a
word at address 0xC3FE_8040, as a half-word at address 0xC3FE_8042, or as a byte at address
0xC3FE_8043.
38.3.2.1 Power Domain Status Register (PCU_PSTAT)
Address 0xC3FE_8040
Access: User read, Supervisor read, Test read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Figure 38-2. Power Domain Status Register (PCU_PSTAT)
This register reflects the power status of all available power domains.
Table 38-3. Power Domain Status Register (PCU_PSTAT) Field Descriptions
Field
PDn Power status for power domain #n
0 Power domain is inoperable
1 Power domain is operable
Description
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
38-3