PXS20RM Datasheet, PDF (928/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Interrupt Controller (INTC)
For example, ISR1 has a priority of 1, ISR2 has a priority of 2, and ISR3 has a priority of 3. They all share
the same resource. Before ISR1 or ISR2 can access that resource, they must raise the PRI value in
INTC_CPR_PRCx to 3, the ceiling of all of the ISR priorities. After they release the resource, they must
lower the PRI value in INTC_CPR_PRCx to prevent further priority inversion. If they do not raise their
priority, then ISR2 can preempt ISR1, and ISR3 can preempt ISR1 or ISR2, possibly corrupting the shared
resource. Another possible failure mechanism is deadlock if the higher priority ISR needs the lower
priority ISR to release the resource before it can continue, but the lower priority ISR can not release the
resource until the higher priority ISR completes and execution returns to the lower priority ISR.
Using the PCP instead of disabling processor recognition of all interrupts reduces the priority inversion
time when accessing a shared resource. For example, while ISR3 can not preempt ISR1 while it is
accessing the shared resource, all of the ISRs with a priority higher than 3 can preempt ISR1.
28.6.6.2 Ensuring coherency
A scenario can exist on some SoC implementations that can cause non-coherent accesses to the shared
resource. As an example, ISR1 and ISR2 both share a resource. ISR1 has a lower priority than ISR2. ISR1
is executing, and it writes to the INTC_CPR_PRC0. The instruction following this store is a store to a
value in a shared coherent data block. Either just before or at the same time as the first store, the INTC
asserts the interrupt request to the processor because the peripheral interrupt request for ISR2 has asserted.
As the processor is responding to the interrupt request from the INTC, and as it is aborting transactions
and flushing its pipeline, it is possible in some SoC implementations that both of these stores will be
executed. ISR2 thereby thinks that it can access the data block coherently, but the data block has been
corrupted.
OSEK uses the GetResource and ReleaseResource system services to manage access to a shared resource.
To prevent this corruption of a coherent data block, modifications to PRI in INTC_CPR_PRC0 can be
made by those system services with the code sequence:
disable processor recognition of interrupts
PRI modification
enable processor recognition of interrupts
28.6.7 Selecting Priorities According to Request Rates and Deadlines
The selection of the priorities for the ISRs can be made using Rate Monotonic Scheduling or a superset of
it, Deadline Monotonic Scheduling. In RMS, the ISRs which have higher request rates have higher
priorities. In DMS, if the deadline is before the next time the ISR is requested, then the ISR is assigned a
priority according to the time from the request for the ISR to the deadline, not from the time of the request
for the ISR to the next request for it.
For example, ISR1 executes every 100 s, ISR2 executes every 200 s, and ISR3 executes every 300 s.
ISR1 has a higher priority than ISR2 which has a higher priority than ISR3. However, if ISR3 has a
deadline of 150 s, then it has a higher priority than ISR2.
The INTC has 16 priorities, which could be much less than the number of ISRs. In this case, the ISRs
should be grouped with other ISRs that have similar deadlines. For example, a priority could be allocated
for every time the request rate doubles. ISRs with request rates around 1 ms would share a priority, ISRs
with request rates around 500 s would share a priority, ISRs with request rates around 250 s would share
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PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor