PXS20RM Datasheet, PDF (65/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Memory Map
Chapter 2
Memory Map
Table 2-1 shows the memory map for the PXS20.
All addresses on the PXS20, including those that are reserved, are identified in the table. The addresses
represent the physical addresses assigned to each region or module name. The table also identifies the
associated peripheral control register (PCTL) number and mode (LS, DP, or both).
All memory not listed in this table is reserved, and access to those locations may produce undesirable
results.
Table 2-1. PXS20 memory map, ordered by start address
Start Address
Size (KB)
PCTL
number
Mode
Region / Module Name
Flash memory
0x0000_0000
16
—
LS/DP Flash-memory array partition 1 (low address) or
test flash memory¹
0x0000_4000
48
—
LS/DP Flash-memory array partition 1 (low address)
0x0001_0000
48
—
LS/DP Flash-memory array partition 1 (low address)
0x0001_C000
16
—
LS/DP Flash-memory array partition 1 (low address)
0x0002_0000
64
—
LS/DP Flash-memory array partition 2 (low address)
0x0003_0000
64
—
LS/DP Flash-memory array partition 2 (low address)
0x0004_0000
128
—
LS/DP Flash-memory array partition 3 (mid address)
0x0006_0000
128
—
LS/DP Flash-memory array partition 3 (mid address)
0x0008_0000
256
—
LS/DP Flash-memory array partition 4 (high address)
0x000C_0000
256
—
LS/DP Flash-memory array partition 4 (high address)
0x00F0_0000 1024
—
LS/DP Shadow block
0x0100_0000 507904
—
LS/DP Flash-memory emulation mapping
Static RAM
0x4000_0000
64
—
DP SRAM
128
0x5000_0000
64
—
LS SRAM
—
DP SRAM²
On-platform 1 peripherals³
0x8FF0_0000
16
—
DP PBRIDGE_1
0x8FF0_4000
16
—
DP XBAR_1
0x8FF1_0000
16
—
DP MPU_1
0x8FF2_4000
16
—
DP Semaphores (SEMA4_1)
0x8FF3_8000
16
—
DP SWT_1
0x8FF3_C000
16
—
DP STM_1
0x8FF4_0000
16
—
DP ECSM_1
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
2-1