PXS20RM Datasheet, PDF (1114/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Nexus Crossbar Slave Port Data Trace Module (NXSS) [cut2/3 only]
Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R _{RWT RWT} 0 0 0 0 0 0 0 0
W1 ²
AMID
NSID
0 0 0 0 _{RC RC} 0 0 0 0 0 0
12
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 33-5. Data Trace Control Register (DTC)
Table 33-5. DTC field descriptions
Bit
RWT1
RWT2
AMID
Description
Read/write trace 1
00 No trace messages generated
X1 Enable data read trace
1X Enable data write trace
Read/write trace 2
00 No trace messages generated
X1 Enable data read trace
1X Enable data write trace
AHB Master ID Select
This field selects which crossbar master will have its accesses to the SRAM traced. Only one
master can have its accesses to the SRAM traced at a time.
Lock-Step Mode Decoding
0000 Core_0 / Core_1
0001 Reserved
0010 eDMA_0 / eDMA_1
0011 FlexRay
0100–1111 Reserved
Decoupled Parallel Mode Decoding
0000 Core_0
0001 Core_1
0010 eDMA_0
0011 FlexRay
0100 Reserved
0101 Reserved
0110 DMA 1
0111 Reserved
1000–1111 Reserved
33-6
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor