PXS20RM Datasheet, PDF (891/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
For a graceful shutdown the application shall perform the following tasks:
1. Disable all enabled message buffers.
a) repeatedly write 1 to FR_MBCCSRn[EDT] until FR_MBCCSRn[EDS] == 0.
2. Stop Protocol Engine.
a) issue HALT command via Protocol Operation Control Register (FR_POCR)
b) wait for POC:halt in Protocol Status Register 0 (FR_PSR0)
26.7.5 Number of Usable Message Buffers
This section describes the relationship between the number of message buffers that can be utilized and the
required minimum CHI clock frequency. Additional constraints for the minimum CHI clock frequency are
given in Section 26.3, Controller Host Interface Clocking.
The CC uses a sequential search algorithm to determine the individual message buffer assigned or
subscribed to the next slot. This search must be finished within one FlexRay slot. The shortest FlexRay
slot is an empty dynamic slot. An empty dynamic slot is a minislot and consists of gdMinislot macroticks
with a nominal duration of gdMacrotick. The minimum duration of a corrected macrotick is
gdMacrotick_min = 39 µT. This results in a minimum slot length of
_slotmin = 39  pdMicrotick  gdMinislot
Eqn. 26-30
The search engine is located in the CHI and runs on the CHI clock. It evaluates one individual message
buffer per CHI clock cycle. For internal status update and double buffer commit operations, and as a result
of the clock domain crossing jitter, an additional amount of 10 CHI clock cycles is required to ensure
correct operation. For a given number of message buffers and for a given CHI clock frequency f_chi, this
results in a search duration of
_search
=
---1----  # MessageBuffers + 10
f_chi
Eqn. 26-31
The message buffer search must be finished within one slot which requires that Equation 26-32 must be
fulfilled
_search  _slotmin
Eqn. 26-32
This results in the formula given in Equation 26-33 which determines the required minimum CHI
frequency for a given number of message buffers that are utilized.
f_chi

--------#----M------e--s---s--a---g---e--B----u---f--f--e---r--s----+-----1---0--------
39  pdMicrotick  gdMinislot
Eqn. 26-33
The minimum CHI frequency for a selected set of relevant protocol parameters is given in Table 26-135.
Table 26-135. Minimum f_chi [MHz] examples (64 message buffers)
pdMicrotick
gdMinislot
[ns]
2
3
4
5
6
7
25.0
37.94
25.30
18.98
15.18
12.65
10.84
50.0
18.98
12.65
9.45
7.59
6.33
5.43
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
26-179