PXS20RM Datasheet, PDF (904/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Frequency-Modulated Phase-Locked Loop (FMPLL)
NOTE
You must ensure that the product of INCTEP and MODPERIOD is less than
(2¹⁵-1) and MODPERIOD is less than or equal to 2¹².
Frequency
md
Center Spread
F0
md
F0
2 × md
Down Spread
T_mod
2T_mod
Figure 27-5. Frequency modulation
Time
27.6.4 Powerdown mode
The FMPLL can be switched off when not required to achieve lower consumption by programming the
ME_x_MC registers in the MC_ME module.
27.7 Requirements
The FMPLL VCO frequency f_VCO, defined in Equation 27-1, must be in the range 256–512 MHz.
f_VCO
=
C_-----L_----K_----I_--N_{---  NDIV}
IDF
Eqn. 27-1
Care is required when programming the multiplication and division factors to respect this requirement.
As a result, the maximum system frequency cannot be reached with all supported (4 MHz to 40 MHz)
XOSC clock frequencies. Before selecting the XOSC clock frequency, you must verify which system
clock frequencies will be supported by the available settings for NDIV, IDF, ODF, and other parameters.
27.8 Recommendations
To avoid any unpredictable behavior of the FMPLL clock, it is recommended to respect the following
guidelines:
• You must change the multiplication, division factors only when the FMPLL output clock is not
selected as the source for an active clock on the chip. MOD_PERIOD, INC_STEP, SPREAD_SEL
bits should be modified before activating the FM modulated mode. Then strobe has to be generated
27-8
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor