PXS20RM Datasheet, PDF (400/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Direct Memory Access (eDMA)
Table 19-1. eDMA 32-bit memory map (continued)
Address offset
Register
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
Reserved
eDMA Enable Request Low (DMAERQL, Channels 15–0)
Reserved
eDMA Enable Error Interrupt Low (DMAEEIL, Channels 15–0)
eDMA Set Enable
Request
(DMASERQ)
eDMA Clear Enable
Request
(DMACERQ)
eDMA Set Enable
Error Interrupt
(DMASEEI)
eDMA Clear Enable
Error Interrupt
(DMACEEI)
eDMA Clear Interrupt
Request
(DMACINT)
eDMA Clear
Error
(DMACERR)
eDMA Set Start Bit
(DMASSRT)
eDMA Clear Done
Status Bit
(DMACDNE)
Reserved
eDMA Interrupt Request Low (DMAINTL, Channels 15–0)
Reserved
eDMA Error Low (DMAERRL, Channels 15–0)
0x0030
0x0034
0x0038–0x00FC
0x0100
0x0104
0x0108
Reserved
eDMA Hardware Request Status Low (DMAHRSL, Channels 15–0)
Reserved
eDMA Channel 0
Priority (DCHPRI0)
eDMA Channel 1
Priority (DCHPRI1)
eDMA Channel 2
Priority (DCHPRI2)
eDMA Channel 3
Priority (DCHPRI3)
eDMA Channel 4
Priority (DCHPRI4)
eDMA Channel 5
Priority (DCHPRI5)
eDMA Channel 6
Priority (DCHPRI6)
eDMA Channel 7
Priority (DCHPRI7)
eDMA Channel 8
Priority (DCHPRI8)
eDMA Channel 9
eDMA Channel 10 eDMA Channel 11
Priority (DCHPRI9) Priority (DCHPRI10) Priority (DCHPRI11)
0x010c
0x0110–0x0FFC
0x1000-0x11FC
0x1200-0x17FC
eDMA Channel 12
Priority (DCHPRI12)
eDMA Channel 13 eDMA Channel 14
Priority (DCHPRI13) Priority (DCHPRI14)
Reserved
TCD0–TCD15
Reserved
eDMA Channel 15
Priority (DCHPRI15)
19.2.1 Register descriptions
19.2.1.1 eDMA Control Register (DMACR)
The 32-bit DMACR defines the basic operating configuration of the eDMA.
The eDMA arbitrates channel service requests. This arbitration can be configured to use either a
fixed-priority or a round-robin selection. In fixed-priority arbitration, the highest priority channel
requesting service is selected to execute. The priorities are assigned by the channel priority registers (see
Section 19.2.1.16, eDMA Channel n Priority (DCHPRIn), n = 0–15). In round-robin arbitration mode, the
channel priorities are ignored and the channels are cycled through without regard to priority.
Minor loop offsets are address offset values added to the final source address (saddr) or destination address
(daddr) upon minor loop completion. When minor loop offsets are enabled, the minor loop offset (mloff)
is added to the final source address (saddr), or the final destination address (daddr), or both prior to the
addresses being written back into the TCD. If the major loop is complete, the minor loop offset is ignored
19-4
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor