PXS20RM Datasheet, PDF (735/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
26.5.2.12 Global Interrupt Flag and Enable Register (FR_GIFER)
Base + 0x0016
Write: Normal Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R _MIF
PRIF
CHIF
WUP
IF
FAFB FAFA
IF IF
RBIF
TBIF
MIE
PRIE
CHIE
WUP
IE
FAFB
IE
FAFA
IE
RBIE
TBIE
W
w1c w1c w1c
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-12. Global Interrupt Flag and Enable Register (FR_GIFER)
This register provides the means to control some of the interrupt request lines and provides the
corresponding interrupt flags. The interrupt flags MIF, PRIF, CHIF, RBIF, and TBIF are the outcome of a
binary OR of the related individual interrupt flags and interrupt enables. The generation scheme for these
flags is depicted in Figure 26-160. For more details on interrupt generation, see Section 26.6.20, Interrupt
Support. These flags are cleared automatically when all of the corresponding interrupt flags or interrupt
enables in the related interrupt flag and enable registers are cleared by the application.
Table 26-17. FR_GIFER field descriptions
Field
MIF
PRIF
CHIF
WUPIF
Description
Module Interrupt Flag — This flag is asserted if at least one of the other interrupt flags in this
register and its related interrupt enable is asserted.
0 No interrupt flag is asserted or no interrupt enable is set
1 At least one of the other interrupt flags in this register is asserted and the related interrupt bit is
asserted, too
Protocol Interrupt Flag — This flag is set if at least one of the individual protocol interrupt flags
in the Protocol Interrupt Flag Register 0 (FR_PIFR0) and Protocol Interrupt Flag Register 1
(FR_PIFR1) is asserted and the related interrupt enable flag is asserted.
0 All individual protocol interrupt flags are equal to 0 or no interrupt enable bit is set.
1 At least one of the individual protocol interrupt flags and the related interrupt enable is equal to
1.
CHI Interrupt Flag — This flag is set if at least one of the individual CHI error flags in the CHI Error
Flag Register (FR_CHIERFR) is asserted and the chi error interrupt enable FR_GIFER[CHIE] is
asserted.
0 All CHI error flags are equal to 0 or the chi error interrupt is disabled
1 At least one CHI error flag is asserted and chi error interrupt is enabled
Wakeup Interrupt Flag — This flag is set when the CC has received a wakeup symbol on the
FlexRay bus. The application can determine on which channel the wakeup symbol was received
by reading the related wakeup flags WUB and WUA in the Protocol Status Register 3 (FR_PSR3).
0 No wakeup condition or interrupt disabled
1 Wakeup symbol received on FlexRay bus and interrupt enabled
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
26-23