PXS20RM Datasheet, PDF (1175/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Power Management Unit (PMU)
Table 39-2. Fault assertion conditions
Fault number
Signal
NCF[13]
LVD BIST OK in test mode/ LVD NOK in user mode
NCF[14]
NCF[15]¹
NCF[16]¹
NCF[17]¹
HVD BIST OK in test mode/ HVD NOK in user mode
LVD VREG fault detected by self-checking
LVD FLASH fault detected by self-checking
LVD IO fault detected by self-checking
CF[21]
LVD/HVD BIST failure result in test mode
NOTES:
1 _{It can only be checked once after destructive reset. Once cleared they will be disabled permanently}
until the next destructive reset
All faults are monitored by the following fields in the PMUCTRL_FAULT register:
• LHCF
• LNCF
• HNCF
Before clearing the HVD and LVD critical fault by means of the FCCU, you must clear the following four
pending fields in the PMUCTRL_IRQS register:
• MLVDP
• BLVDP
• MHVDP
• BHVDP
The critical fault number will be kept asserted as long as one of these fields is '1'.
When the PMU enters LVD or HVD test mode, it is not allowed to enter STOP mode. If the device enters
stop mode after the pending status pin has been set it is not possible to reset it by SW until the CPU clock is
stopped.
The PMU can assert two faults on FLASH voltage monitor, two faults on IO voltage monitor and two
faults on Regulator voltage monitor (corresponding to failure of either the main or backup LVDs). They
are asserted (active low) during the power up phase, if a rising edge is not detected on the related LVD.
Each fault from the PMU sets:
• Its corresponding pending bit inside the PMUCTRL_IRQS register. If the associated interrupt in
the PMUCTRL_IRQE register is enabled, the PMU will send an IRQ to the INTC.
• Its corresponding non critical fault
39.7 Memory map and register description
The PMU memory map is shown in Table 39-3.
The PMU registers are mapped into the MC_PCU address space (base address: 0xC3FE_8080).
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
39-5