PXS20RM Datasheet, PDF (508/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Fault Collection and Control Unit (FCCU)
Field
OPR
Table 22-3. FCCU_CTRL field descriptions (continued)
Description
Operation run
00000 No operation [OP0].
00001 Set the FCCU into the CONFIG state [OP1].
00010 Set the FCCU into the NORMAL state [OP2].
00011 Read the FCCU state (refer to the FCCU_STAT register) [OP3].
00100 Read the FCCU frozen status flags [OP4].
00101 Read the FCCU frozen status flags [OP5].
00110 Read the FCCU frozen status flags [OP6].
00111 Read the FCCU frozen status flags [OP7].
01000 Read the FCCU frozen status flags [OP8].
01001 Read the CF status register (refer to the FCCU_CFS register) [OP9].
01010 Read the NCF status register (refer to the FCCU_NCFS register) [OP10].
01011 CF status clear operation in progress (refer to the FCCU_CFS register) [OP11].
01100 NCF status clear operation in progress (refer to the FCCU_NCFS register) [OP12].
01101 Clear the freeze status registers (refer to the freeze registers) [OP13].
01110 CONFIG to NORMAL FCCU state (configuration timeout) in progress [OP14].
01111 Clear the operation status (OPS = Idle, NVML = 0) [OP15].
10000 Lock the FCCU configuration [OP16].
10001 Read the ALARM timer (refer to the FCCU_XTMR register) [OP17].
10010 Read the SMRT timer (refer to the FCCU_XTMR register) [OP18].
10011 Read the CFG timer (refer to the FCCU_XTMR register) [OP19].
10100–11111 Reserved [OP20–OP30].
11111 Run the NVM loading operation (only for test purposes) [OP31].
The software must not modify the OPR field until the completion of the operation (any write
operation will be ignored until then). After the operation has been completed, the OPS field is set
and the OPR field is automatically cleared (OPR = 000).
Your software must not program the following opcodes:
• OP11 and OP12 (these opcodes are automatically selected when the FCCU_CFS or
FCCU_NCFS registers are cleared by a write-clear operation into the related register)
• OP14 (This opcode is automatically selected when the timeout occurs [FCCU_CFG_TO] during
the configuration procedure. In this case, the FCCU state is automatically forced in NORMAL
mode setting the default configuration. In this phase any write operation to the FCCU
configuration registers is inhibited.)
• OP20–OP30 (these are reserved; if you attempt to use them, they will return an ABORT
response without any side effect)
The ABORT response occurs in the following cases:
• wrong access (missing or wrong key) to the FCCU_CFS register (clear operation OP11)
• wrong access (missing or wrong key) to the FCCU_NCFS register (clear operation OP12)
• wrong access (missing or wrong key) to the FCCU_CTRL register (OP1, OP2, OP16 operation)
• OP1 (CONFIG command) execution when FCCU state  NORMAL or configuration locked
• OP20–OP30 (RESERVED operations) execution
The OP31 opcode executes the NVM configuration loading via the software. It should be used only
for test/debug purposes.
22.6.2 FCCU CTRL Key Register (FCCU_CTRLK)
The FCCU_CTRLK register implements the key access for the operations OP1, OP2, OP16, OP31
according to the following sequence:
1. Write the key into the FCCU_CTRLK register.
22-8
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor