PXS20RM Datasheet, PDF (1097/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Mode Entry Module (MC_ME)
CAUTION
It is illegal to switch the flash from low-power mode to power-down mode
and from power-down mode to low-power mode. The MC_ME, however,
does not prevent this nor does it flag it.
32.4.3.8 Pad Outputs-On
On completion of the step, if the PDO bit of the ME_<target mode>_MC register is cleared, then
• all pad outputs are enabled to return to their previous state
• the I/O pads power sequence driver is switched on
32.4.3.9 Peripheral Clocks Enable
Based on the current and target device modes, the peripheral configuration registers ME_RUN_PC0…7,
ME_LP_PC0…7, and the peripheral control registers ME_PCTL0…143, the MC_ME enables the clocks
for selected modules as required. This step is executed only after the process is completed.
32.4.3.10 Processor and Memory Clock Enable
If the mode transition is from any of the low-power modes HALT0 or STOP0 to RUN0…3, the clocks to
the processor and system memory are enabled. The process of enabling these clocks is executed only after
the Flash Module Switch-On process is completed.
32.4.3.11 Processor Low-Power Mode Exit
If the mode transition is from any of the low-power modes HALT0 orSTOP0 to RUN0…3, the MC_ME
requests the processor to exit from its halted or stopped state. This step is executed only after the Processor
and Memory Clock Enable process is completed.
32.4.3.12 System clock switching
Based on the SYSCLK bit field of the ME_<current mode>_MC and ME_<target mode>_MC registers,
if the target and current system clock configurations differ, the following method is implemented for clock
switching.
• The target clock configuration for the 16 MHz int. RC osc. takes effect only after the S_IRCOSC
bit of the register is set by hardware (i.e. the 16 MHz internal RC oscillator has stabilized).
• For cut2/3: The target clock configuration for the 4-40 MHz crystal osc. takes effect only after the
S_XOSC bit of the register is set by hardware (i.e., the 4-40 MHz crystal oscillator has stabilized).
• The target clock configuration for the system FMPLL takes effect only after the S_PLL0 bit of the
register is set by hardware (i.e. the system FMPLL has stabilized).
• If the clock is to be disabled, the SYSCLK bit field should be programmed with “1111”. This is
possible only in theTEST mode.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
32-41