PXS20RM Datasheet, PDF (802/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
If the application writes 1 to the EDT bit, no write access to the other register bits is performed.
If the application writes 0 to the EDT bit and 1 to the LCKT bit, no write access to the other bits is
performed.
Table 26-89. FR_MBCCSRn Field Descriptions
Field
Description
MCM
MBT
MTD
CMT
EDT
LCKT
MBIE
Message Buffer Configuration
Message Buffer Commit Mode — This bit configures the commit mode of a double buffered
message buffer.
0 Streaming commit mode
1 Immediate commit mode
Message Buffer Type — This bit configures the buffering type of a transmit message buffer.
0 Single buffered message buffer
1 Double buffered message buffer
Message Buffer Transfer Direction — This bit configures the transfer direction of a message
buffer.
0 Receive message buffer
1 Transmit message buffer
Message Buffer Control
Commit for Transmission — This bit indicates if the transmit message buffer data are ready for
transmission.
0 Message buffer data not ready for transmission
1 Message buffer data ready for transmission
Enable/Disable Trigger — If the application writes 1 to this bit, a message buffer enable or disable
is triggered, depending on the current value EDS status bit is 0.
0 No effect
1 Message buffer enable or disable is triggered
Lock/Unlock Trigger — If the application writes 1 to this bit, a message buffer lock or unlock is
triggered, depending on the current value of the LCKS status bit.
0 No effect
1 Message buffer lock or unlock is triggered
Message Buffer Interrupt Enable — This control bit defines whether the message buffer will
generate an interrupt request when its MBIF flag is set.
0 Interrupt request generation disabled
1 Interrupt request generation enabled
26-90
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor