PXS20RM Datasheet, PDF (1017/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Field
DIV_M
LIN Controller (LINFlexD)
Table 31-23. LINIBRR field descriptions
Description
LFDIV mantissa
These bits define the LINFlexD divider (LFDIV) mantissa value (see Table 31-24).
This register can be written in Initialization mode only.
Table 31-24. Integer baud rate selection
DIV_M
0x0
0x1
...
0xFFFFE
0xFFFFF
Mantissa
LIN clock disabled
1
...
1048574
1048575
31.10.12 LIN checksum field register (LINCFR)
Offset: 0x2C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0 0 0 0 0
CF
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 31-29. LIN checksum field register (LINCFR)
Field
CF
Table 31-25. LINCFR field descriptions
Description
Checksum bits
When LINCR1[CCD] is cleared, these bits are read-only. When LINCR1[CCD] is set, these bits are
read/write. See Table 31-11.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
31-41