PXS20RM Datasheet, PDF (759/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

26.5.2.34 Sync Frame Table Offset Register (FR_SFTOR)
FlexRay Communication Controller
Base + 0x0042
Write: POC:config
0
R
W
Rese
t
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
SFT_OFFSET[15:1]
000000000000000
Figure 26-34. Sync Frame Table Offset Register (FR_SFTOR)
This register defines the FlexRay memory area related offset for sync frame tables. For more details, see
Section 26.6.12, Sync Frame ID and Sync Frame Deviation Tables.
Table 26-39. FR_SFTOR Field Description
Field
Description
SFT_OFFSET Sync Frame Table Offset — The offset of the Sync Frame Tables in the FlexRay memory area.
This offset is required to be 16-bit aligned. Thus STF_OFFSET[0] is always 0.
26.5.2.35 Sync Frame Table Configuration, Control, Status Register
(FR_SFTCCSR)
Base + 0x0044
Write: Normal Mode
0
1
2
R0
0
W _ELKT
OLK
T
3
4
5
6
CYCNUM
7
8
9
10
11
12
13
14
15
ELKS
OLK
S
EVAL OVAL
0
0
SDV SID
EN EN
OPT
Rese
t
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-35. Sync Frame Table Configuration, Control, Status Register (FR_SFTCCSR)
This register provides configuration, control, and status information related to the generation and access
of the clock sync ID tables and clock sync measurement tables. For a detailed description, see
Section 26.6.12, Sync Frame ID and Sync Frame Deviation Tables.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
26-47