PXS20RM Datasheet, PDF(639/1368 Page) Freescale Semiconductor, Inc – PXS20 Microcontroller

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PXS20RM Datasheet, PDF (639/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

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FlexCAN Module

Peripheral Clock (FMPLL)

CPI Clock

Prescaler

(1 .. 256)

Sclock

Oscillator Clock (Xtal)

CLK_SRC

Figure 24-14. CAN Engine Clocking Scheme

The crystal oscillator clock should be selected whenever a tight tolerance (up to 0.1%) is required in the

CAN bus timing. The crystal oscillator clock has better jitter performance than FMPLL generated clocks.

NOTE

This clock selection feature may not be available in all MCUs. A particular

MCU may not have a FMPLL, in which case it would have only the

oscillator clock, or it may use only the FMPLL clock feeding the FlexCAN

module. In these cases, the CLK_SRC bit in the CTRL Register has no

effect on the module operation.

In order to guarantee reliable operation, the selected CAN Protocol Interface

(CPI) clock should not be faster as the the peripheral clock.

The FlexCAN module supports a variety of means to setup bit timing parameters that are required by the

CAN protocol. The Control Register has various fields used to control bit timing parameters: PRESDIV,

PROPSEG, PSEG1, PSEG2 and RJW. See Section 24.3.4.2, Control Register (CTRL).

The PRESDIV field controls a prescaler that generates the Serial Clock (Sclock), whose period defines the

âtime quantumâ used to compose the CAN waveform. A time quantum is the atomic unit of time handled

by the CAN engine.

fTq= ï¨---P----r---e---s----cf--C-a---A-l-e-N---r-C---ÃL---K--V----a---l--u----e---ï©-

A bit time is subdivided into three segments1 (reference Figure 24-15 and Table 24-9):

â¢ SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are expected to

happen within this section

â¢ Time Segment 1: This segment includes the Propagation Segment and the Phase Segment 1 of the

CAN standard. It can be programmed by setting the PROPSEG and the PSEG1 fields of the CTRL

Register so that their sum (plus 2) is in the range of 4 to 16 time quanta

1. For further explanation of the underlying concepts please refer to ISO/DIS 11519â1, Section 10.3. Reference also the

Bosch CAN 2.0A/B protocol specification dated September 1991 for bit timing.

Freescale Semiconductor

PXS20 Microcontroller Reference Manual, Rev. 1

24-39

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