PXS20RM Datasheet, PDF (1266/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Self-Test Control Unit (STCU)
42.4.2 Register conventions
The following bus operations (contiguous byte enables) are supported:
• Word (32 bits) data read operations
• Word (32 bits) data write operation for write-enabled registers
The registers of the STCU are accessible in each access mode: user or supervisor. Reading and writing to
reserved areas results in unexpected behavior.
42.4.3 Detailed register descriptions
42.4.3.1 STCU SK Code Register (STCU_SKC) [cut2/3 only]
The STCU_SKC register implements the security key code mechanism needed to access in write mode to
the other STCU registers. In order to unlock the STCU access after:
• The Power-On, Destructive or External Reset
• The completation of the STCU run
the SW (IPs bus) or the SSCM interfaces have to apply the following sequence:
• write the key1 into the STCU_SKC register
• write the key2 into the STCU_SKC register
After the Self-Test sequence has been completed or the Bypass feature has been enabled ( setting the bit
BYP into the STCU_CFG), the SSCM interface is no longer available.
In case of invalid access or sequence (Key1/2 have to be applied consecutively), a transfer error on the IPS
or SSCM bus is asserted depending on the selected source. The STCU write access is locked and to unlock
the access the sequence has to be applied again.
In case the STCU register access last more cycles than the one defined into the Hard-coded WDG time-out,
the STCU write access is locked and the WDG and Register ITF clocks are switched off. Also in this case,
in order to enable again the write access to the STCU and the WDG and Register ITF clocks, it is required
to apply again the sequence.
The STCU_SKC register is not readable. The value 0x00000000 is always returned in case of a read
operation.
42-8
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor