PXS20RM Datasheet, PDF (486/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Error Correction Status Module (ECSM)
21.4.2.11 ECC Error Generation Register (EEGR)
The ECC Error Generation Register is a 16-bit control register used to force the generation of single- and
double-bit data inversions in the memories with ECC, most notably the platform RAM. This capability is
provided for two purposes:
• It provides a software-controlled mechanism for “injecting” errors into the memories during data
writes to verify the integrity of the ECC logic.
• It provides a mechanism to allow testing of the software service routines associated with memory
error logging.
Platform flash memory includes an ECC logic check to verify the integrity of its ECC logic (see
Section 23.1.5.12, ECC logic check).
For platform RAM, the intent is to generate errors during data write cycles, such that subsequent reads of
the corrupted address locations generate ECC events, either single-bit corrections or double-bit
non-correctable errors that are terminated with an error response.
The enabling of these error generation modes requires the same SoC-configurable input enable signal (as
that used to enable single-bit correction reporting) be asserted.
See Figure 21-10 and Table 21-12 for the ECC Configuration Register definition.
Register address: ECSM Base + 0x004A
0
1
2
3
4
R _{FRCA 0 FRC1 FR11 0}
W^P
BI
BI
RESET: ₀
0
0
0
0
5
6
7
8
0 FRCN FR1 0
CI NCI
0
0
0
0
9
10 11 12 13 14 15
ERRBIT[0:6]
0
0
0
0
0
0
0
= Unimplemented
Figure 21-10. ECC Error Generation (EEGR) Register
Name
FRCAP
Table 21-12. ECC Error Generation (EEGR) Field Descriptions
Description
Force Platform RAM Error Injection Access Protection
0 = All masters are able to generate platform RAM ECC errors via the EEGR register.
1 = Only the master defined with as having hmaster=0 (usually the core) can generate platform RAM
ECC errors via the EEGR register.
The assertion of this bit ensures that platform RAM data inversions can only occur from the master
module with the master ID of 0. Since this is usually the core, this protects the platform RAM from
errant or multiple simultaneous attempted data inversions from other master modules and, in the case
of a multi-core system, ensures that only one core can issue a platform RAM data inversion.
The reset value of the bit is 0 and as a result, platform RAM data inversions can be requested from
any master module. It is the responsibility of the software to ensure the proper setting of this bit.
21-12
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor