PXS20RM Datasheet, PDF (595/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flash Memory
Field
ARBM
MxPFD
MxAP
Table 23-27. PFAPR field descriptions
Description
Arbitration Mode. This 2-bit field controls the arbitration for PFLASH controllers supporting 2 AHB
ports. The port arbitration mode is used only when accesses from the 2 AHB ports attempt to
simultaneously reference the same flash memory array.
00 Fixed priority arbitration with AHB p0 > p1
01 Fixed priority arbitration with AHB p1 > p0
1X Round-robin arbitration
Master x Prefetch Disable (x = 0,1,2,...,7). These bits control whether prefetching may be triggered
based on the master number of the requesting AHB master. This field is further qualified by the
PFCRn[B02_Px_DPFE, B02_Px_IPFE, Bx_Py_BFE] bits.
0 Prefetching may be triggered by this master
1 No prefetching may be triggered by this master
Master x Access Protection (x = 0,1,2,...,7). These fields control whether read and write accesses
to the flash are allowed based on the master number of the initiating module.
00 No accesses may be performed by this master
01 Only read accesses may be performed by this master
10 Only write accesses may be performed by this master
11 Both read and write accesses may be performed by this master
23.2.3 Functional description
The PFLASH2P has two AHB-Lite slave ports and a single flash array interface. The dual ported design
of the PFLASH2P enables efficient use of a single flash memory array by two processor cores. Each AHB
port has dedicated line buffers to support single-cycle read accesses and to limit accesses to the flash array.
The PFLASH2P generates read and write enables, the flash array address, write size, and write data as
inputs to the flash array controller. The PFLASH2P captures read data from the flash array interface and
drives it onto the proper AHB port. If line buffering is enabled, when data is read from the array it is stored
in a line buffer. Up to four lines of data (128 bits) are buffered by the PFLASH2P for each AHB port.
If pre-fetching is enabled, data is read in advance and stored in the line buffers allowing single-cycle (zero
AHB wait-states) read data responses on buffer hits. Prefetch triggering may be restricted to instruction
accesses only, data accesses only, or may be unrestricted. Prefetch triggering may also be controlled on a
per-master basis.
Arbitration between the two AHB ports for access to the flash interface is primarily based on the type of
access; writes have priority over reads which have priority over prefetches. If both ports are doing the same
type of access, priority is based on the settings of the arbitration and priority bits in the PFCRP0 register.
23.2.3.1 Basic interface protocol
The PFLASH2P interfaces to the flash array by driving addresses and read or write enable signals.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
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