PXS20RM Datasheet, PDF (381/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

e200z4d Core Complex Overview
Table 17-4. Interrupt Registers (continued)
Register
Description
MCSRR1 Machine check save/restore register 1—Saves machine state on machine check interrupts and
restores those values when an rfmci instruction is executed
Syndrome Registers
MCSR
Machine check syndrome register—Saves machine check syndrome information on machine check
interrupts.
ESR
Exception syndrome register—Provides a syndrome to differentiate among the different kinds of
exceptions that generate the same interrupt type. Upon generation of a specific exception type, the
associated bits are set and all other bits are cleared.
SPE Interrupt Registers
SPEFSCR Signal processing and embedded floating-point status and control register—Provides interrupt control
and status as well as various condition bits associated with the operations performed by the SPE. See
Table 17-5 for a list of the associated IVORs.
Other Interrupt Registers
DEAR
Data exception address register—Contains the address that was referenced by a load, store, or cache
management instruction that caused an alignment, data TLB miss, or data storage interrupt.
IVPR
IVORs
Together, IVPR[32–47] || IVORn [48–59] || 0b0 define the address of an interrupt-processing routine.
See Table 17-5 for more information.
MSR
Machine state register—Defines the state of the processor. When an interrupt occurs, it is updated to
preclude unrecoverable interrupts from occurring during the initial portion of the interrupt handler
Each interrupt has an associated interrupt vector address, obtained by concatenating IVPR[32–47] with the
address index in the associated IVOR (that is, IVPR[32–47] || IVORn[48–59] || 0b0). The resulting
address is that of the instruction to be executed when that interrupt occurs. IVPR and IVOR values are
indeterminate on reset and must be initialized by the system software using mtspr.
Table 17-5 lists IVOR registers implemented on the e200z4d and the associated interrupts.
Table 17-5. Exceptions and conditions
IVORn
None¹
0²
1
2
3
4²
5
6
7
8
Interrupt Type
System reset (not an interrupt)
Critical input
Machine check
Machine check (non-maskable interrupt)
Data storage
Instruction storage
External input
Alignment
Program
Floating-point unavailable
System call
IVORn
Interrupt Type
9
10
11
12
13
14
15
16–31
32
33
34
AP unavailable (not used by this core)
Decrementer
Fixed-interval timer
Watchdog timer
Data TLB error
Instruction TLB error
Debug
Reserved
SPE unavailable
SPE data exception
SPE round exception
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
17-11