PXS20RM Datasheet, PDF (576/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flash Memory
Table 23-11. UT0 Field Descriptions
Field
Description
31
UTE
U-Test Enable. This status bit gives indication when U-Test is enabled. All bits in UT0, UT1, UT2, UM0,
UM1, UM2, UM3, and UM4 are locked when this bit is 0. This bit is not writeable to a 1, but may be
cleared. The reset value is 0. The method to set this bit is to provide a password, and if the password
matches, the UTE bit is set to reflect the status of enabled, and is enabled until it is cleared by a register
write. The UTE password will only be accepted if MCR[PGM] = 0 and MCR [ERS] = 0 (program and
erase are not being requested). UTE can only be cleared if UT0[AID] = 1, UT0[AIE] and UT0[EIE] = 0.
While clearing UTE, writes to set AIE or set EIE will be ignored. For UTE, the password 0xF9F9_9999
must be written to the UT0 register.
31
SBCE
Single Bit Correction Enable. SBC enables Single Bit Correction results to be observed in MCR[SBC].
Also is used as an enable for interrupt signals created by the c90fl module. ECC corrections that occur
when SBCE is cleared will not be logged.
0 Single Bit Corrections observation is disabled.
1 Single Bit Correction observation is enabled.
29–24 Reserved, reset to 0.
23-16 Data Syndrome Input. These bits enable checks of ECC logic by allowing check bits to be input into the
DSI[7:0] ECC logic and then read out by doing array reads or array integrity checks. The DSI[7:0] correspond to
the 8 ECC check bits on a double word.
15-6 Reserved, reset to 0.
5
MRE
Margin Read Enable. MRE combined with MRV enables Factory Margin Reads to be done. Margin reads
are only active during Array Integrity Checks. Normal user reads are not affected by MRE. MRE is not
writable if AID is low.
0 Margin reads are not enabled.
1 Margin reads are enabled during Array Integrity Checks.
4
MRV
Margin Read Value. MRV selects the margin level that is being checked. Margin can be checked to an
erased level (MRV=1) or to a programmed level (MRV=0). In order for this value to be valid, MRE must
also be set. MRV is not writable if AID is low.
0 Zero’s margin reads are requested.
1 One’s margin reads are requested.
3
ECC Data Input Enable. EIE enables the input registers (DSI and DAI) to be the source of data for the
EIE array. This is useful in the ECC logic check. If this bit is set, data read thru a BIU read request will be
from the DSI and DAI registers when an address match is achieved to the ADR register. EIE is not
simultaneously writable to a 1 as UTI is being cleared to a 0.
0 Data read is from the flash array.
1 Data read is from the DSI and DAI registers.
2
Array Integrity Sequence. AIS determines the address sequence to be used during array integrity
AIS checks. The default sequence (AIS = 0) is meant to replicate sequences normal “user” code follows, and
thoroughly checks the read propagation paths. This sequence is proprietary. The alternative sequence
(AIS = 1) is just logically sequential. It should be noted that the time to run a sequential sequence is
significantly shorter than the time to run the proprietary sequence. If MRE is set, AIS has no effect.
0 Array integrity sequence is proprietary sequence.
1 Array integrity sequence is sequential.
23-26
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor