PXS20RM Datasheet, PDF (882/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
The read access is handled by the PE internal CPU with the lowest execution priority. This may cause an
response delay with a maximum of 1000 PE clock cycle (25us).
26.6.22.2 PE DRAM Write Access
A write access into the PE DRAM can be initiated in any protocol state. The following sequence describes
a write access to the PE DRAM address 0x70.
1. FR_PEDRAR:= 0x30E0; // INST=0x3; ADDR=0x70
2. wait until FR_PEDRAR[DAD] == 1; // wait for end of PE DRAM access
3. val = FR_PEDRDR[DATA]; // get read back PE DRAM data
The write access is handled by the PE internal CPU with the lowest execution priority. This may causes
an response delay with a maximum of 1000 PE clock cycle (25us).
If the conditions given in Section 26.6.22.3, PE DRAM Write Access Limitations, are fulfilled, the data
provided in PE DRAM Data Register (FR_PEDRDR) are written into the PE DRAM, read back in the next
clock cycle and stored into the PE DRAM Data Register (FR_PEDRDR). Otherwise, data are not written
into the PE DRAM and 0x0000 is stored into the PE DRAM Data Register (FR_PEDRDR).
26.6.22.3 PE DRAM Write Access Limitations
The PE DRAM is used by the protocol engine if the module is not in POC:default config state. The only
address not used by the protocol engine is 0x70. To prevent the corruption of protocol engine data the
following PE DRAM write access limitations apply for application writes.
1. When the module is in POC:default config state, all PE DRAM addresses are writable.
2. When the module is not in POC:default config state, only PE DRAM address 0x70 is writable.
26.6.23 CHI Lookup-Table Memory (CHI LRAM)
The CHI Lookup-Table Memory (CHI LRAM) is an CHI internal memory which contains the message
buffer configuration data. The configuration data for two message buffers are contained in one memory
row. The CHI LRAM is divided into 6 memory BANKs.
Table 26-129. CHI LRAM Layout
ADR
BANK5
BANK4
BANK3
BANK2
BANK1
BANK0
0x00 FR_MBIDXR1
0x01 FR_MBIDXR3
FR_MBFIDR1
FR_MBFIDR3
0x0F FR_MBIDXR63 FR_MBFIDR63
FR_MBCCFR1
FR_MBCCFR3
...
MBCCF63
FR_MBIDXR0
FR_MBIDXR2
FR_MBIDXR62
FR_MBFIDR0
FR_MBFIDR2
MBFID62
FR_MBCCFR0
FR_MBCCFR2
FR_MBCCFR62
The CHI LRAM is accessed by the application via regular register read and write accesses.
26-170
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor