PXS20RM Datasheet, PDF (376/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

e200z4d Core Complex Overview
— OTM facilitates ownership trace by providing visibility of which process ID or operating
system task is activated.An ownership trace message is transmitted when a new process/task is
activated, allowing the development tool to trace ownership flow.
— Allows enhanced download/upload capabilities.
• Data acquisition messaging
— Allows code to be instrumented to export customized information to the Nexus auxiliary output
port.
• Watchpoint messaging by means of the auxiliary interface
• Watchpoint trigger enable of program and/or data trace messaging
• Run-time access to the processor memory map by means of the JTAG port
All features are controllable and configurable by means of the JTAG port.
17.3 Programming model
This section describes the register model, instruction model, and the interrupt model as they are defined
by the Power ISA, Freescale EIS, and the e200z4d implementation.
17.3.1 Register set
Figure 17-2 and Figure 17-3 show the complete e200z4d register set, including the sets of the registers that
are accessible in supervisor mode and the set of registers that are accessible in user mode. The number to
the right of the special-purpose registers (SPRs) is the decimal number used in the instruction syntax to
access the register. For example, the integer exception register (XER) is SPR 1.
Figure 17-2 shows the registers that can be accessed by supervisor-level software. User-level software can
access only those registers listed in Figure 17-3.
17-6
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor