PXS20RM Datasheet, PDF (1308/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Software Watchdog Timer (SWT)
Offset 0x010
Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
WSC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 45-5. SWT Service Register (SWT_SR)
Table 45-6. SWT_SR Field Descriptions
Field
Description
WSC
Watchdog Service Code.This field is used to service the watchdog and to clear the soft lock bit
(SWT_CR[SLK]). If the SWT_CR[KEY] bit is set, two pseudorandom key values are written to service the
watchdog, see Section 45.4 for details. Otherwise, the sequence 0xA602 followed by 0xB480 is written to
the WSC field. To clear the soft lock bit (SWT_CR[SLK]), the value 0xC520 followed by 0xD928 is written to
the WSC field.
45.3.2.6 SWT Counter Output Register (SWT_CO)
The SWT Counter Output (SWT_CO) register is a read only register that shows the value of the internal
down counter when the SWT is disabled.
CAUTION
Do not access the SWT_CO register in Lock Step Mode (LSM).
Offset 0x014
Access: Read Only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 45-6. SWT Counter Output Register (SWT_CO)
Table 45-7. SWT_CO Register Field Descriptions
Field
Description
CNT
Watchdog Count. When the watchdog is disabled (SWT_CR[WEN]=0) this field shows the value of the
internal down counter. When the watchdog is enabled the value of this field is 0x0000_0000. Values in this
field can lag behind the internal counter value for up to six system plus eight counter clock cycles.
Therefore, the value read from this field immediately after disabling the watchdog may be higher than the
actual value of the internal counter.
45-6
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor