PXS20RM Datasheet, PDF (963/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Memory Protection Unit (MPU)
Offset MPU_Base + 0x400 + (16*n) + 0x0 (MPU_RGDn.Word0)
Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
SRTADDR
W
00000
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 30-5. MPU Region Descriptor, Word 0 Register (MPU_RGDn.Word0)
Table 30-6. MPU_RGDn.Word0 field descriptions
Field
Description
0–26 Start Address. This field defines the most significant bits of the 0-modulo-32 byte start address of the
SRTADDR memory region.
30.6.4.2 MPU Region Descriptor n, Word 1 (MPU_RGDn.Word1)
The second word of the MPU region descriptor defines the 31-modulo-32 byte end address of the memory
region. Writes to this word clear the region descriptor’s valid bit (see Section 30.6.4.4, MPU Region
Descriptor n, Word 3 (MPU_RGDn.Word3), for more information).
Offset MPU_Base + 0x400 + (16*n) + 0x4 (MPU_RGDn.Word1)
Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ENDADDR
W
11111
Reset
(n=0)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Reset
(n>0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
Figure 30-6. MPU Region Descriptor, Word 1 Register (MPU_RGDn.Word1)
Table 30-7. MPU_RGDn.Word1 field descriptions
Field
Description
0–26 End Address. This field defines the most significant bits of the 31-modulo-32 byte end address of the
ENDADDR memory region. There are no hardware checks to verify that ENDADDR >= SRTADDR; it is software’s
responsibility to properly load these region descriptor fields.
30.6.4.3 MPU Region Descriptor n, Word 2 (MPU_RGDn.Word2)
The third word of the MPU region descriptor defines the access control rights of the memory region. Bus
masters 0-3 have a 6-bit field defining separate privilege rights for user and supervisor mode accesses as
well as the optional inclusion of a process identification field within the definition. For these fields, the
bus master number refers to the logical master number as specified in Section 15.1.4, Logical master IDs.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
30-9