PXS20RM Datasheet, PDF (491/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Error Correction Status Module (ECSM)
Register address: ECSM Base + 0x0057
0
1
2
3
4
5
6
7
R
WRITE
SIZE
PROTECTION
W
RESET:
-
-
-
-
-
-
-
-
= Unimplemented
Figure 21-13. Platform Flash Memory ECC Attributes (PFEAT) Register
Table 21-15. PFEAT field descriptions
Field
WRITE
SIZE
PROTECTION
Description
AMBA-AHB HWRITE
0 = AMBA-AHB read access
1 = AMBA-AHB write access
AMBA-AHB HSIZE[0:2]
0b000 = 8-bit AMBA-AHB access
0b001 = 16-bit AMBA-AHB access
0b010 = 32-bit AMBA-AHB access
0b1xx = Reserved
AMBA-AHB HPROT[0:3]
Protection[3]: Cacheable 0 = Non-cacheable,1 = Cacheable
Protection[2]: Bufferable 0 = Non-bufferable,1 = Bufferable
Protection[1]: Mode 0 = User mode, 1 = Supervisor mode
Protection[0]: Type 0 = I-Fetch, 1 = Data
21.4.2.15 Platform Flash Memory ECC Data Registers (PFEDRL and PFEDRH)
These two 32-bit registers contain a 64-bit field, PFEDR, for capturing the data associated with the last,
properly-enabled ECC event in the platform flash memory. Depending on the state of the ECC
Configuration Register, an ECC event in the platform flash memory causes the address, attributes and data
associated with the access to be loaded into the PFEAR, PFEMR, PFEAT, PFEDRH, and PFEDRL
registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register to be asserted.
The data captured on a multi-bit non-correctable ECC error is undefined.
These registers can only be read from the IPS programming model; any attempted write is ignored. If no
flash memory ECC event is defined to be handled for this module, accesses to these registers will terminate
with an error.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
21-17