PXS20RM Datasheet, PDF (596/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flash Memory
Accesses are terminated based on timing parameters contained in the PFCR0. The correct setting of the
wait-state control bits in the PFCR0 is determined by the access time of the flash array and the platform
clock frequency.
The PFLASH2P also has the capability of extending the normal AHB access timing by inserting additional
wait states for reads. This capability is provided to allow emulation of other memories which have different
access time characteristics. These wait-states are applied in addition to the normal wait-states incurred for
flash accesses. Refer to Section 23.2.3.6, Wait-state emulation for more detail on wait-state emulation.
Prefetching of next sequential line can be blocked. Buffer hits can be blocked as well, regardless of
whether the access corresponds to valid data in one of the line read buffers. These steps are taken to ensure
that timing emulation is correct and that excessive prefetching is avoided.
23.2.3.2 Read cycles
Read cycles from the flash array are initiated by driving a valid access address and then asserting a read
enable. The PFLASH2P then waits for the flash array to provide read data. This data is normally stored in
the least-recently updated line read buffer in parallel with the requested data being forwarded to the AHB.
Single clock read responses to the AHB are possible with the PFLASH2P when the requested read access
is buffered. In these cases, read data is returned to the AHB data phase with a zero wait-state response.
23.2.3.3 Write cycles
Write cycles to the flash array are initiated by driving a valid access address, driving write data, and
indicating the size of the write data.The PFLASH2P then waits for the indicated number of wait states
before the cycle has terminated.
23.2.3.4 Flash error response operation
The flash array may signal an error response. This may occur due to an uncorrectable ECC error, or
because of improper sequencing during program/erase operations. When an error response is received, the
PFLASH2P will not update or validate a line read buffer. An error response may be signaled on read or
write operations.
23.2.3.5 Line Read Buffers and Prefetch Operation
The PFLASH2P contains four read buffers per AHB port which are used to hold line and ECC data read
from the flash array. Each buffer operates independently, and is filled using a single array access. The
buffers are used for both prefetch and normal demand fetches.
Prefetch triggering is controllable on a per-master and access-type basis. Bus masters may be enabled or
disabled from triggering prefetches, and triggering may be further restricted based on whether a read
access is for instruction or data. A read access to the PFLASH2P may trigger a prefetch to the next
sequential line of array data on the cycle following the request. The access address is incremented to the
next-higher 16 byte boundary, and a flash array prefetch is initiated if the data is not already resident in a
line read buffer. Prefetched data is always loaded into the least-recently-used buffer.
Buffers may be in one of six states, listed here in prioritized order:
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PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor