PXS20RM Datasheet, PDF (364/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
an external SPI master. If the TFUF bit is set while the TFUF_RE bit in the DSPI_RSER is set, an interrupt
request is generated.
16.4.6.5 Receive FIFO Drain Interrupt or DMA Request
The Receive FIFO Drain Request indicates that the RX FIFO is not empty. The Receive FIFO Drain
Request is generated when the number of entries in the RX FIFO is not zero, and the RFDF_RE bit in the
DSPI_RSER is set. The RFDF_DIRS bit in the DSPI_RSER selects whether a DMA request or an
interrupt request is generated.
16.4.6.6 Receive FIFO Overflow Interrupt Request
The Receive FIFO Overflow Request indicates that an overflow condition in the RX FIFO has occurred.
A Receive FIFO Overflow request is generated when RX FIFO and shift register are full and a transfer is
initiated. The RFOF_RE bit in the DSPI_RSER must be set for the interrupt request to be generated.
Depending on the state of the ROOE bit in the DSPI_MCR, the data from the transfer that generated the
overflow is either ignored or shifted in to the shift register. If the ROOE bit is set, the incoming data is
shifted in to the shift register. If the ROOE bit is cleared, the incoming data is ignored.
16.4.7 Power Saving Features
The DSPI supports two power-saving strategies:
• External Stop mode
• Module Disable mode - Clock gating of non-memory mapped logic
16.4.7.1 .Stop Mode (External Stop Mode)
The DSPI supports the stop mode protocol. When a request is made to enter external stop mode, the DSPI
block acknowledges the request . If a serial transfer is in progress, the DSPI waits until it reaches the frame
boundary before it is ready to have its clocks shut off .While the clocks are shut off, the DSPI
memory-mapped logic is not accessible. The states of the interrupt and DMA request signals cannot be
changed while in External Stop mode.
16.4.7.2 Module Disable Mode
Module disable mode is a block-specific mode that the DSPI can enter to save power. Host CPU can
initiate the module disable mode by setting the MDIS bit in the DSPI_MCR.
When the MDIS bit is set, the DSPI negates Clock Enable signal at the next frame boundary. If
implemented, the Clock Enable signal can stop the clock to the non-memory mapped logic. When Clock
Enable is negated, the DSPI is in a dormant state, but the memory mapped registers are still accessible.
Certain read or write operations have a different effect when the DSPI is in the module disable mode.
Reading the RX FIFO Pop Register does not change the state of the RX FIFO. Likewise, writing to the TX
FIFO Push Register does not change the state of the TX FIFO. Clearing either of the FIFOs has no effect
in the module disable mode. Changes to the DIS_TXF and DIS_RXF fields of the DSPI_MCR have no
effect in the module disable mode. In the module disable mode, all status bits and register flags in the DSPI
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PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor