PXS20RM Datasheet, PDF (968/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Memory Protection Unit (MPU)
Offset MPU_Base + 0x800 + (4*n) (MPU_RGDAACn)
Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 1 15 16 17 18 19 2 21 22 23 24 25 2 27 28 29 30 31
4
0
6
R0 0 0 0 0 0 0 0M
M
M
M
3 M3S M3UM 2 M2S M2UM 1 M1S M1UM 0 M0S M0UM
P M r w xP M r w xP M r w xP M r w x
W
E
E
E
E
Reset
(n=0)
0
0
0
0
0
0
0
0
0
1
1
0
0
00
1
1
0
0
0
01
1
0
0
0
00
0
0
0
0
Reset
(n>0)
0
0
0
0
0
0
0
0
0
0
0
0
0
00
0
0
0
0
0
00
0
0
0
0
00
0
0
0
0
Figure 30-9. MPU RGD Alternate Access Control n (MPU_RGDAACn)
Since the MPU_RGDAACn register is simply another memory mapping for MPU_RGDn.Word2, the field
definitions shown in Table 30-10 are identical to those presented in Table 30-8.
Table 30-10. MPU_RGDAACn field descriptions
Field
M3PE
M3SM
M3UM
M2PE
M2SM
M2UM
Description
Bus master 3 process identifier enable. If set, this flag specifies that the process identifier and mask
(defined in MPU_RGDn.Word3) are to be included in the region hit evaluation. If cleared, then the
region hit evaluation does not include the process identifier.
Bus master 3 supervisor mode access control. This 2-bit field defines the access controls for bus
master 3 when operating in supervisor mode. The M3SM field is defined as:
0b00 r, w, x = read, write and execute allowed
0b01 r, –, x = read and execute allowed, but no write
0b10 r, w, – = read and write allowed, but no execute
0b11 Same access controls as that defined by M3UM for user mode
Bus master 3 user mode access control. This 3-bit field defines the access controls for bus master 3
when operating in user mode. The M3UM field consists of three independent bits, enabling read, write
and execute permissions: {r,w,x}. If set, the bit allows the given access type to occur; if cleared, an
attempted access of that mode may be terminated with an access error (if not allowed by any other
descriptor) and the access not performed.
Bus master 2 process identifier enable. If set, this flag specifies that the process identifier and mask
(defined in MPU_RGDn.Word3) are to be included in the region hit evaluation. If cleared, then the
region hit evaluation does not include the process identifier.
Bus master 2 supervisor mode access control. This 2-bit field defines the access controls for bus
master 2 when operating in supervisor mode. The M2SM field is defined as:
0b00 r, w, x = read, write and execute allowed
0b01 r, –, x = read and execute allowed, but no write
0b10 r, w, – = read and write allowed, but no execute
0b11 Same access controls as that defined by M2UM for user mode
Bus master 2 user mode access control. This 3-bit field defines the access controls for bus master 2
when operating in user mode. The M2UM field consists of three independent bits, enabling read, write
and execute permissions: {r,w,x}. If set, the bit allows the given access type to occur; if cleared, an
attempted access of that mode may be terminated with an access error (if not allowed by any other
descriptor) and the access not performed.
30-14
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor