PXS20RM Datasheet, PDF (256/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Cross-Triggering Unit (CTU)
• First command bit (only for CTU internal use);
• Interrupt request bit (only for CTU internal use).
13.5.3 ADC results
ADC results can be stored in the channel relevant standard result register and/or in one of the 4 FIFOs: the
different FIFOs allow to dispatch ADC results according to the type of acquisition (ex: phase currents,
rotor position, ground-noise, other). Each FIFO has its own interrupt line and DMA request signal (plus
an individual overflow error bit in the FIFO status register). The store location is specified in the ADC
command, i.e. the FIFOs are available only in CTU Control Mode. Each entry of a FIFO is 32-bits. The
size of the FIFOs are the following: FIFO1 & FIFO2: 16 entries (sized to avoid overflow during a full
PWM period for current acquisitions); FIFO3 & FIFO4: 4 entries (low acquisition rate FIFOs). Results in
each FIFO can be read by 16 bits read transaction (only the result is read in order to minimize the CPU
load before computing on results) or by 32 bits read transaction (both the result and the channel number
are read in order to avoid blind acquisitions), 5 bits in the upper 16 bits indicate the ADC unit (1 bit) and
the channel number (4 bits). The result registers (only for the FIFOs) can be read from 2 different addresses
in the ADC memory map. The format of the result depends on the address from which it is read. The
available formats are
• Unsigned right-justified
(conversion result is unsigned right-justified data, i.e. bits [9:0] are used for 10-bit resolution and
bits [15:10] always return zero when read).
• Signed left-justified
(conversion result is signed left-justified data, i.e. bit [15] is reserved for sign and is always read
as zero for this ADC, bits [14:5] are used for 10-bit resolution and bits [4:0] always return zero
when read).
13.6 Reload mechanism
Some CTU registers are double-buffered, and the reload is controlled by a reload enable bit, as the
TGSISR_RE bit or the DFE bit, but for the most of the double-buffered registers, the reload is controlled
by the MRS occurrence, and it is synchronized with the beginning of the CTU control period.
If the MRS occurs while the user is updating some double-buffered registers, eg. some registers of the
Triggers List, the new Triggers List will be a mix of the old Triggers List and the new Triggers List,
because the user has not ended the update of the Triggers List before the MRS occurrence.
In order to avoid this case, one bit is used to enable the reload operation, i.e. to inform the CTU that the
user has ended updates to the double-buffered registers, and the reload can be performed without problems
of mixed scenarios. In order to guarantee the coherency, the reload of all double-buffered registers is
enabled by setting GRE (General Reload Enable) bit in the CTU Control Register. The user must ensure
that all intended double-buffered registers are updated before a new MRS occurrence. If an MRS occurs
before a GRE bit is set (e.g. wrong application timing), the update is not performed, the previous values
of all double-buffered registers remain active, the error flag is set (the MRS_RE bit in the CTU Error Flag
Register) and, if enabled, CTU performs an interrupt request.
13-10
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor