PXS20RM Datasheet, PDF (360/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
SCK (CPOL = 0)
SCK (CPOL = 1)
Master SOUT
Master SIN
PCSx
t_CSC
t_ASC t_{DT tCSC}
t_CSC = PCS to SCK delay
t_ASC = After SCK delay
t_DT = Delay after Transfer (minimum CS negation time)
Figure 16-31. Example of Non-Continuous Format (CPHA=1, CONT=0)
When the CONT bit = 1, the PCS signal remains asserted for the duration of the two transfers. The Delay
between Transfers (t_DT) is not inserted between the transfers. Figure 16-32 shows the timing diagram for
two four-bit transfers with CPHA = 1 and CONT = 1.
SCK (CPOL = 0)
SCK (CPOL = 1)
Master SOUT
Master SIN
PCS
t_CSC
t_CSC = PCS to SCK delay
t_ASC = After SCK delay
t_ASC t_CSC
Figure 16-32. Example of Continuous Transfer (CPHA=1, CONT=1)
You must fill the TXFIFO with the number of entries that will be concatenated together under one PCS
assertion for both master and slave before the TXFIFO becomes empty. For example: While transmitting
in master mode, you should ensure that the last entry in the TXFIFO, after which TXFIFO becomes empty,
must have the CONT bit in command frame as deasserted (i.e. CONT bit = 0).While operating in slave
mode, it should be ensured that when the last-entry in the TXFIFO is completely transmited (i.e. the
16-40
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor