PXS20RM Datasheet, PDF (574/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flash Memory
HBS register functions are shown in Table 23-9.
Table 23-9. HBS Field Descriptions
Field
Description
0-25 Reserved, reset to 0.
26-31 High Address Space Block Select. High Address Block Select has the same characteristics as LSEL.
HSEL[5:0]
23.1.6.7 Address Register (ADR)
The Address register (ADR) provides the first failing address in the event module failures (ECC or
PGM/Erase state machine)
Offset 0x0018
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R _{SAD 0}
0
0
0
0
0
0
0
0
0
ADDR
W
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ADDR
0
0
0
W
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 23-9. ADR Register
ADR register functions are shown in Table 23-10.
Table 23-10. ADR Field Descriptions
Field
0
SAD
1-10
Description
Shadow Address. The SAD bit qualifies the address captured during an ECC Event Error, Single Bit
Correction, or State Machine operation.
The SAD register is not writable.
0 Address Captured is from Main Array Space.
1 Address Captured is from Shadow Array Space.
Reserved, reset to 0.
23-24
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor