PXS20RM Datasheet, PDF (1129/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Nexus Port Controller (NPC)
34.3.2.1 EVTO - Event Out
Event Out (EVTO) is an output pin that is asserted upon breakpoint occurrence to provide breakpoint
status indication. The EVTO output of the NPC is generated based on the values of the individual EVTO
signals from all Nexus blocks that implement the signal.
34.3.2.2 JCOMP - JTAG Compliancy
The JCOMP signal provides the ability to share the TAP. The NPC TAP controller is enabled when JCOMP
is set to the NPC enable encoding, otherwise the NPC TAP controller remains in reset.
34.3.2.3 MDO - Message Data Out
Message Data Out (MDO) are output pins used for uploading OTM, BTM, DTM, and other messages to
the development tool. The development tool should sample MDO on the rising edge of MCKO. The width
of the MDO bus used is determined by reset configuration.
34.3.2.4 MSEO_B - Message Start/End Out
Message Start/End Out (MSEO) is an output pin that indicates when a message on the MDO pins has
started, when a variable length packet has ended, or when the message has ended. The development tool
should sample MSEO on the rising edge of MCKO.
34.3.2.5 TCK - Test Clock Input
Test Clock Input (TCK) pin is used to synchronize the test logic and control register access through the
JTAG port.
The JTAG Clock (TCK) typically operates at a frequency well below the system clock frequency, as
specified in the electrical data sheets. In some cases, however, such as low power mode (if the device
supports low power modes), the system clock frequency may be lowered significantly from the normal
operating range. If the system clock frequency is reduced below the frequency of TCK it will no longer be
possible to communicate with the Nexus Port Controller Port Configuration Register (NPC_PCR).
Therefore, if the tool needs to update the NPC_PCR Low Power Debug Enable (NPC[PCR[LP_DBG]) or
Low Power Synchronization bits (NPC[PCR[LP1_SYN] and NPC[PCR[LP2_SYN]), the clock frequency
must be lowered.
Ensure that the frequency of TCK does not exceed the system clock frequency during normal operation
and during low power operation.
NOTE
TCK clock frequency needs to be smaller than SYSCLK/2 for correct
operation of NPC/Nexus/NXSS subsystem
34.3.2.6 TDI - Test Data Input
Test Data Input (TDI) pin receives serial test instruction and data. TDI is sampled on the rising edge of
TCK.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
34-5