PXS20RM Datasheet, PDF (50/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Introduction
phase wait states may also occur if the slave being accessed is not parked on the requesting master in the
crossbar.
Table 1-2 shows the number of additional data phase wait states required for a range of memory accesses.
Table 1-2. Platform Memory Access Time Summary
AHB transfer
e200z4d instruction fetch
e200z4d instruction fetch
e200z4d data read
e200z4d data write
e200z4d data write
e200z4d data write
e200z4d flash memory read
e200z4d flash memory read
Data phase
wait states
Description
0
Flash memory prefetch buffer hit (page hit)
3
Flash memory prefetch buffer miss
(based on 4-cycle random flash array access time)
0–1
SRAM read
0
SRAM 32-bit write
0
SRAM 64-bit write (executed as 2 x 32-bit writes)
0–2
SRAM 8-,16-bit write
(Read-modify-Write for ECC)
0
Flash memory prefetch buffer hit (page hit)
3
Flash memory prefetch buffer miss (at 120 MHz; includes 1 cycle
of program flash memory controller arbitration)
1.4.10 Error Correction Status Module (ECSM)
The ECSM on this device manages the ECC configuration and reporting for the platform memories (flash
memory and SRAM). It does not implement the actual ECC calculation. A detected error (double error for
flash memory or SRAM) is also reported to the FCCU. The following errors and indications are reported
into the ECSM dedicated registers:
• ECC error status and configuration for flash memory and SRAM
• ECC error reporting for flash memory
• ECC error reporting for SRAM
• ECC error injection for SRAM
1.4.11 Peripheral Bridge (PBRIDGE)
The PBRIDGE implements the following features:
• Duplicated periphery
• Master access right per peripheral (per master: read access enable; write access enable)
• Write buffering for peripherals
• Checker applied on PBRIDGE output toward periphery
• Byte endianess swap capability
1-10
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor