PXS20RM Datasheet, PDF (363/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
16.4.6 Interrupts/DMA Requests
The DSPI has several conditions that can only generate interrupt requests and two conditions that can
generate interrupt or DMA request. Table 16-24 lists these conditions.
Table 16-24. Interrupt and DMA Request Conditions
Condition
End of Queue (EOQ)
TX FIFO Fill
Transfer Complete
TX FIFO Underflow
RX FIFO Drain
RX FIFO Overflow
Flag
EOQF
TFFF
TCF
TFUF
RFDF
RFOF
Interrupt
X
X
X
X
X
X
DMA
X
X
Each condition has a flag bit in the DSPI Status Register (DSPI_SR) and an Request Enable bit in the DSPI
DMA/Interrupt Request Select and Enable Register (DSPI_RSER). The TX FIFO Fill Flag (TFFF) and
RX FIFO Drain Flag (RFDF) generate interrupt requests or DMA requests depending on the TFFF_DIRS
and RFDF_DIRS bits in the DSPI_RSER.
The DSPI module also provides a global interrupt request line, which is asserted when any of individual
interrupt requests lines is asserted.
16.4.6.1 End of Queue Interrupt Request
The End of Queue Request indicates that the end of a transmit queue is reached. The End of Queue Request
is generated when the EOQ bit in the executing SPI command is set and the EOQF_RE bit in the
DSPI_RSER is set.
16.4.6.2 Transmit FIFO Fill Interrupt or DMA Request
The Transmit FIFO Fill Request indicates that the TX FIFO is not full. The Transmit FIFO Fill Request is
generated when the number of entries in the TX FIFO is less than the maximum number of possible entries,
and the TFFF_RE bit in the DSPI_RSER is set. The TFFF_DIRS bit in the DSPI_RSER selects whether
a DMA request or an interrupt request is generated.
16.4.6.3 Transfer Complete Interrupt Request
The Transfer Complete Request indicates the end of the transfer of a serial frame. The Transfer Complete
Request is generated at the end of each frame transfer when the TCF_RE bit is set in the DSPI_RSER.
16.4.6.4 Transmit FIFO Underflow Interrupt Request
The Transmit FIFO Underflow Request indicates that an underflow condition in the TX FIFO has
occurred. The transmit underflow condition is detected only for the DSPI, operating in slave mode and SPI
configuration. The TFUF bit is set when the TX FIFO of a DSPI is empty, and a transfer is initiated from
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
16-43