PXS20RM Datasheet, PDF (881/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
Table 26-127. FlexRay Channel Bit Rate Control
FlexRay
Channel
Bit Rate
[Mbit/s]
FR_MCR.BITR
ATE
10.0
000
25.0
12.5
2
8
5
8.0
011
25.0
12.5
2
10
6
5.0
001
25.0
25.0
1
8
5
2.5
010
50.0
50.0
1
8
5
NOTE
The bit rate of 8 Mbit/s is not defined by the FlexRay Communications
System Protocol Specification, Version 2.1 Rev A.
26.6.22 PE Data Memory (PE DRAM)
The PE Data Memory (PE DRAM) is 128 word, 16-bit wide memory with byte access, which contains the
program data of the PE internal CPU. The PE DRAM is divided into two banks, 8-bit each. The memory
data [7:0] are assigned to BANK0, the memory data [15:8] are assigned to BANK1.
Table 26-128. PE DRAM Layout
ADDR
0x00
0x01
0x7F
BANK1
byte1
byte3
...
byte255
BANK0
byte0
byte2
byte254
The FlexRay module provides means to access the PE DRAM from the application. The PE DRAM
application access is initiated and controlled via PE DRAM Access Register (FR_PEDRAR) and PE
DRAM Data Register (FR_PEDRDR). This functionality is used to check the memory error detection.
26.6.22.1 PE DRAM Read Access
A read access from the PE DRAM can be initiated in any protocol state. The following sequence describes
a read access from the PE DRAM address 0x70.
1. FR_PEDRAR:= 0x00E0; // INST=0x0; ADDR=070
2. wait until FR_PEDRAR[DAD] == 1; // wait for end of PE DRAM access
3. val = FR_PEDRDR[DATA]; // get read PE DRAM data
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
26-169