PXS20RM Datasheet, PDF (598/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flash Memory
They can also be configured with a fixed partition between buffers allocated to instruction or data accesses.
For the fixed partition, two configurations are supported. In one configuration, buffers 0 and 1 are allocated
for instruction fetches and buffers 2 and 3 for data accesses. In the second configuration, buffers 0, 1 and
2 are allocated for instruction fetches and buffer 3 reserved for data accesses. In this configuration data
prefetching is disabled.
23.2.3.5.4 Buffer invalidation
The line read buffers may be invalidated under hardware and software control. Assertion of the fl_invbuf
input signal causes the line read buffers to be marked as invalid. To ensure that stale data is not read from
the buffers, software should invalidate the buffers after writing to the array. This is done by clearing the
PFCRPx[BFEN] bit, which also disables the buffers. Software may then restore the PFCRPx[BFEN] bit
to its previous state, and the buffers will have been invalidated.
Also, the buffers are invalidated by hardware on any non-sequential (NSEQ) access with a non-zero wait
state value to support wait-state emulation.
23.2.3.6 Wait-state emulation
Emulation of other memory array timings are supported by the PFLASH2P on read cycles to the flash. This
functionality may be useful to maintain the access timing for blocks of memory which were used to overlay
flash blocks for the purpose of system calibration or tuning during code development.
The PFLASH2P inserts additional wait-states according to the values of the PFCR0 Read Wait State
Control fields plus the value on the address line bits 28-24. Wait-states are applied to the initial access of
a burst fetch or to single-beat read accesses on the AHB system bus.
NOTE
There is an inherent 2-cycle delay added when using non-zero values for
address line bits 28-24.
When the address line bits 28-24 are non-zero, normal AHB termination is extended only for read cycles.
Write cycles are not affected. In addition, no line read buffer prefetches are initiated, and buffer hits are
ignored. See the description of the Read Wait State Control field in the PFCR0 register for further
information on read wait states.
Wait states are applied to the initial access of a burst fetch or to single-beat read accesses on the AHB
system bus.
Table 23-28. Additional wait-state encoding
Memory address
flash address + 0x0000_0000
flash address + 0x0100_0000
flash address + 0x0200_0000
flash address + 0x0300_0000
flash address + 0x0400_0000
flash address + 0x0500_0000
Additional wait-stats
0
10
18
26
3
11
23-48
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor