PXS20RM Datasheet, PDF (1269/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Self-Test Control Unit (STCU)
Field
CFSF
NCFSF
SIRSF
(cut1)
WDTO
ENGE
INVP
Table 42-5. STCU_ERR field descriptions
Description
Critical Faults Status Flag
This flag reports the global status of the CF.
0: No errors that trigger the CF condition occurred.
1: At least one error that triggers the CF condition occurred.
Non Critical Faults Status Flag
0: No errors that trigger the NCF condition occurred.
1: At least one error that triggers the NCF condition occurred.
Stay In Reset Faults Status Flag
0: No Errors which trigger the SIR condition
1: There are Errors which trigger the SIR condition
In the typical condition, it should not be possible to read the content of this register when this bit is
set because the system should be permanently under reset. However, for diagnostic purposes, the
system could exit from reset to allow SW to check the flag and attempt to trace the failure.
Watchdog timeout
0: The self test completed within the assigned watchdog time.
1: The self test did not complete within the assigned watchdog time. This bit is also set when the
STCU is activated but the self test is not run.
Engine Error
0: Valid Engine execution
1: Invalid Engine execution.
Invalid pointer
0: Valid linked pointer list
1: Invalid linked pointer list. The following conditions set this bit:
• Initial LBIST or MBIST pointer is out of range
• LBIST is selected when MBIST is concurrently running or vice versa
• Error in the LBIST/MBIST linking (execution generates an infinite loop)
42.4.3.4 STCU Error Key Register (STCU_ERRK) [cut2/3 only]
The STCU_ERRK register, available on cut2/3 only, implements the security key code to access to the
STCU_ERR register. In order to write the STCU_ERR register, software must:
• Write the keyx into the STCU_ERRK
• Set/clear the STCU_ERR register
wher:e
• Key1 allows to clear the bit at 1
• Key2 allows to set the bit at 0
In case of invalid access, a transfer error on the IPS or SSCM bus is asserted (it depends on the selected
bus interface) and the key is cleared. To unlock the set/clear operation on the STCU_ERR register the
Key1 or Key2 has to be applied again.
Only one access mode (set/clear) at the time is allowed. The last key written into this register defines the
access mode.
In case the STCU register access last more cycles than the one defined into the hard-coded watchdog
time-out or there is a transfer error or the IPS or SSCM bus operation performed just after the Key1/Key2
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
42-11