PXS20RM Datasheet, PDF (181/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Analog-to-Digital Converter (ADC)
9.3.17.2 Self Test Configuration Register 2 (STCR2)
Address: Base + 0x344
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0
0
0
0000
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
000
00
W
EN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Figure 9-26. Self Test Configuration Register 2 (STCR2)
Table 9-28. STCR2 field descriptions
Field
Description
MSKWDSERR
Interrupt enable (STSR1[WDSERR] status bit)
0 Interrupt disabled
1 Enables the STSR1[WDSERR] status bit to generate an interrupt
SERR
Error fault injection control. Setting this bit causes the STSR1[ERRn] status bits to be set.
MSKWDTERR
Interrupt enable (STSR1[WDTERR] status bit)
0 Interrupt disabled
1 Enables the STSR1[WDTERR] status bit to generate an interrupt
MSKST_EOC
Interrupt Enable bit for STSR1[ST_EOC]
0 Interrupt disabled
1 If IMR[MSKEOC] = 1, enables the STSR1[ST_EOC] status bit to generate an interrupt
indication
MSKWDG_EOA_C Interrupt enable (STSR1[WDG_EOA_C] status bit)
0 Interrupt disabled
1 Enables the STSR1[WDG_EOA_C] status bit to generate an interrupt
MSKWDG_EOA_RC Interrupt enable (STSR1[WDG_EOA_RC] status bit)
0 Interrupt disabled
1 Enables the STSR1[WDG_EOA_RC] status bit to generate an interrupt
MSKWDG_EOA_S Interrupt enable (STSR1[WDG_EOA_S] status bit)
0 Interrupt disabled
1 Enables the STSR1[WDG_EOA_S] status bit to generate an interrupt
MSKERR_C
Interrupt enable (STSR1[ERR_C] status bit)
0 Interrupt disabled
1 Enables the STSR1[ERR_C] status bit to generate an interrupt
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
9-23