PXS20RM Datasheet, PDF (769/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
26.5.2.47 Slot Status Counter Condition Register (FR_SSCCR)
Base + 0x0066
16-bit write access required
Write: Anytime
0
R0
W WMD
Rese
t
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
SEL
CNTCFG MCY VFR SYF NUF SUF STATUSMASK[3:0]
000000000000000
Figure 26-47. Slot Status Counter Condition Register (FR_SSCCR)
This register is used to access and program the four internal non-memory mapped Slot Status Counter
Condition Registers FR_SSCCR0 to FR_SSCCR3. Each of these four internal slot status counter condition
registers defines the mode and the conditions for incrementing the counter in the corresponding Slot Status
Counter Registers (FR_SSCR0–FR_SSCR3). The correspondence is given in Table 26-55. For a detailed
description of slot status counters, refer to Section 26.6.18.4, Slot Status Counter Registers.
Table 26-54. FR_SSCCR Field Descriptions
Field
WMD
SEL
CNTCFG
MCY
VFR
Description
Write Mode — This control bit defines the write mode of this register.
0 Write to all fields in this register on write access.
1 Write to SEL field only on write access.
Selector — This field selects one of the four internal slot counter condition registers for access.
00 select FR_SSCCR0.
01 select FR_SSCCR1.
10 select FR_SSCCR2.
11 select FR_SSCCR3.
Counter Configuration — These bit field controls the channel related incrementing of the slot status
counter.
00 increment by 1 if condition is fulfilled on channel A.
01 increment by 1 if condition is fulfilled on channel B.
10 increment by 1 if condition is fulfilled on at least one channel.
11 increment by 2 if condition is fulfilled on both channels channel.
increment by 1 if condition is fulfilled on only one channel.
Multi Cycle Selection — This bit defines whether the slot status counter accumulates over multiple
communication cycles or provides information for the previous communication cycle only.
0 The Slot Status Counter provides information for the previous communication cycle only.
1 The Slot Status Counter accumulates over multiple communication cycles.
Valid Frame Restriction — This bit is used to restrict the counter to received valid frames.
0 The counter is not restricted to valid frames only.
1 The counter is restricted to valid frames only.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
26-57