PXS20RM Datasheet, PDF (775/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
26.5.2.53 Receive FIFO System Memory Base Address Register
(FR_RFSYMBADR)
Base + 0x00E8
Write: Disabled Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
SMBA[31:16]
W
Rese
t
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-53. Receive FIFO System Memory Base Address High Register (FR_RFSYMBADHR)
Base + 0x00EA
Write: Disabled Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
SMBA[15:4]
W
0000
Rese
t
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-54. Receive FIFO System Memory Base Address Low Register (FR_RFSYMBADLR)
These registers define the system memory base address for the receive FIFO if the FIFO address mode bit
FR_MCR[FAM] is set to 1. The system memory base address is used by the BMIF to calculate the physical
memory address for system memory accesses for the FIFOs.
Table 26-61. FR_RFSYMBADR Field Descriptions
Field
SMBA
Description
System Memory Base Address — This is the value of the system memory base address for the
receive FIFO if the FIFO address mode bit FR_MCR[FAM] is set to 1. It is defines as a byte address.
26.5.2.54 Receive FIFO Periodic Timer Register (FR_RFPTR)
Base + 0x00EC
Write: POC:config
0
R0
W
Rese
t
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
PTD
000000000000000
Figure 26-55. Receive FIFO Periodic Timer Register (FR_RFPTR)
This register holds periodic timer duration for the periodic FIFO timer. The periodic timer applies to both
FIFOs (see Section 26.6.9.3, FIFO Periodic Timer).
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
26-63