PXS20RM Datasheet, PDF (343/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
Table 16-13. DSPI_PUSHR field descriptions in master mode
Field
CONT
CTAS
Descriptions
Continuous Peripheral Chip Select Enable. The CONT bit selects a Continuous Selection Format. The
bit is used in SPI master mode. The bit enables the selected PCS signals to remain asserted between
transfers. See Section 16.4.4.5, Continuous selection format, for more information.
0 Return Peripheral Chip Select signals to their inactive state between transfers
1 Keep Peripheral Chip Select signals asserted between transfers
Clock and Transfer Attributes Select. The CTAS field selects number of the DSPI_CTAR register be
used to set the transfer attributes for the associated SPI frame. The field is only used in SPI master
mode. In SPI slave mode DSPI_CTAR0 is used. The number of DSPI_CTAR registers is
implementation specific and the CTAS should be set to select only implemented one.
EOQ
End Of Queue. The EOQ bit provides a means for host software to signal to the DSPI that the current
SPI transfer is the last in a queue. At the end of the transfer the EOQF bit in the DSPI_SR is set.
0 The SPI data is not the last data to transfer
1 The SPI data is the last data to transfer
CTCNT
Clear Transfer Counter. The CTCNT bit clears the SPI_TCNT field in the DSPI_TCR register. The
SPI_TCNT field is cleared before transmission of the current SPI frame begins.
0 Do not clear SPI_TCNT field in the DSPI_TCR
1 Clear SPI_TCNT field in the DSPI_TCR
PUSHR_PE Parity Enable. PE bit enables parity bit transmission and parity reception check for the SPI frame
(for cut2/3 only) 0 No parity bit included/checked.
1 Parity bit is transmitted instead of last data bit in frame, parity checked for received frame.
PUSHR_PP Parity Polarity. PP bit controls polarity of the parity bit transmitted and checked
(for cut2/3 only) 0 Even Parity: number of “1” bits in the transmitted frame is even. The DSPI_SR[SPEF] bit is set if in
the received frame number of “1” bits is odd.
1 Odd Parity: number of “1” bits in the transmitted frame is odd. The DSPI_SR[SPEF] bit is set if in
the received frame number of “1” bits is even.
PCSx
Peripheral Chip Select 0–7. The PCS bits select which PCS signals will be asserted for the transfer.
0 Negate the PCS[x] signal
1 Assert the PCS[x] signal
TXDATA
Transmit Data. The TXDATA field holds SPI data to be transferred according to the associated SPI
command.
Address: DSPI_BASE + 0x34
Access:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
TXDATA[31:16]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
TXDATA[15:0]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 16-16. DSPI PUSH TX FIFO Register (DSPI_PUSHR) in slave mode
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
16-23