PXS20RM Datasheet, PDF (1002/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

LIN Controller (LINFlexD)
Table 31-12. LIN master break length selection (continued)
MBL
Length
1111
50-bit
SLEEP
1
x
0
Table 31-13. Operating mode selection
INIT
Operating mode
0
Sleep (reset value)
1
Initialization
0
Normal
31.10.2 LIN interrupt enable register (LINIER)
Offset: 0x04
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
SZIE OCIE BEIE CEIE HEIE 0 0 FEIE BOIE LSIE
DRIE DTIE HRIE
W w1c w1c w1c w1c w1c
w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 31-19. LIN interrupt enable register (LINIER)
Field
SZIE
OCIE
BEIE
CEIE
Table 31-14. LINIER field descriptions
Description
Stuck at Zero Interrupt Enable
0: No interrupt when SZF bit in LINESR or UARTSR is set
1: Interrupt generated when SZF bit in LINESR or UARTSR is set
Output Compare Interrupt Enable
0: No interrupt when OCF bit in LINESR or UARTSR is set
1: Interrupt generated when OCF bit in LINESR or UARTSR is set
Bit Error Interrupt Enable
0: No interrupt when BEF bit in LINESR is set
1: Interrupt generated when BEF bit in LINESR is set
Checksum Error Interrupt Enable
0: No interrupt on Checksum error
1: Interrupt generated when checksum error flag (CEF) is set in LINESR
31-26
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor