PXS20RM Datasheet, PDF (1077/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Mode Entry Module (MC_ME)
Table 32-9. Invalid Mode Transition Status Register (ME_IMTS) Field Descriptions (continued)
Field
S_NMA
S_SEA
Description
Non-existing Mode Access status — This bit is set whenever the target mode requested is one of
those non existing modes determined by ME_ME register. It is cleared by writing a ‘1’ to this bit.
0 Target mode requested is an existing mode
1 Target mode requested is a non-existing mode
SAFE Event Active status — This bit is set whenever the device is in SAFE mode, SAFE event bit
is pending and a new mode requested other than RESET/SAFE modes. It is cleared by writing a ‘1’
to this bit.
0 No new mode requested other than RESET/SAFE while SAFE event is pending
1 New mode requested other than RESET/SAFE while SAFE event is pending
32.3.2.7 Debug Mode Transition Status Register (ME_DMTS)
Address 0xC3FD_C018
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
PREVIOUS_MODE
0000
00
00
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
00
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 32-11. Debug Mode Transition Status Register (ME_DMTS)
This register provides the status of different factors which influence mode transitions. It is used to give an
indication of why a mode transition indicated by ME_GS.S_MTRANS may be taking longer than
expected.
NOTE
The ME_DMTS register does not indicate whether a mode transition is
ongoing. Therefore, some ME_DMTS bits may still be asserted after the
mode transition has completed.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
32-21