PXS20RM Datasheet, PDF (341/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
Table 16-12. DSPI_RSER field descriptions
Field
Description
TCF_RE
Transmission Complete Request Enable. The TCF_RE bit enables TCF flag in the DSPI_SR to
generate an interrupt request.
0 TCF interrupt requests are disabled
1 TCF interrupt requests are enabled
EOQF_RE
DSPI Finished Request Enable. The EOQF_RE bit enables the EOQF flag in the DSPI_SR to
generate an interrupt request.
0 EOQF interrupt requests are disabled
1 EOQF interrupt requests are enabled
TFUF_RE
Transmit FIFO Underflow Request Enable. The TFUF_RE bit enables the TFUF flag in the DSPI_SR
to generate an interrupt request.
0 TFUF interrupt requests are disabled
1 TFUF interrupt requests are enabled
TFFF_RE
Transmit FIFO Fill Request Enable. The TFFF_RE bit enables the TFFF flag in the DSPI_SR to
generate a request. The TFFF_DIRS bit selects between generating an interrupt request or a DMA
requests.
0 TFFF interrupt requests or DMA requests are disabled
1 TFFF interrupt requests or DMA requests are enabled
TFFF_DIRS Transmit FIFO Fill DMA or Interrupt Request Select. The TFFF_DIRS bit selects between generating
a DMA request or an interrupt request. When the TFFF flag bit in the DSPI_SR is set, and the
TFFF_RE bit in the DSPI_RSER register is set, this bit selects between generating an interrupt
request or a DMA request.
0 Interrupt request will be generated
1 DMA request will be generated
SPEF_RE
(for cut2/3
only)
SPI Parity Error Request Enable. The SPEF_RE bits enables SPEF flag in the DSPI_SR to generate
an interrupt requests.
0 PEF interrupt requests are disabled
1 PEF interrupt requests are enabled
RFOF_RE
Receive FIFO Overflow Request Enable. The RFOF_RE bit enables the RFOF flag in the DSPI_SR
to generate an interrupt requests.
0 RFOF interrupt requests are disabled
1 RFOF interrupt requests are enabled
RFDF_RE
Receive FIFO Drain Request Enable. The RFDF_RE bit enables the RFDF flag in the DSPI_SR to
generate a request. The RFDF_DIRS bit selects between generating an interrupt request or a DMA
request.
0 RFDF interrupt requests or DMA requests are disabled
1 RFDF interrupt requests or DMA requests are enabled
RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select. The RFDF_DIRS bit selects between
generating a DMA request or an interrupt request. When the RFDF flag bit in the DSPI_SR is set, and
the RFDF_RE bit in the DSPI_RSER register is set, the RFDF_DIRS bit selects between generating
an interrupt request or a DMA request.
0 Interrupt request will be generated
1 DMA request will be generated
16.3.2.7 DSPI PUSH TX FIFO Register (DSPI_PUSHR)
The DSPI_PUSHR register provides means to write to the TX FIFO. Data written to this register is
transferred to the TX FIFO. See Section 16.4.2.4, Transmit First In First Out (TX FIFO) Buffering
Mechanism for more information. Eight or sixteen bit write accesses to the DSPI_PUSHR transfers all 32
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
16-21